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data sheet ics831721agi revision a august 19, 2011 1 ?2011 integrated device technology, inc. differential clock/data multiplexer ICS831721I general description the ICS831721I is a high-performance, differential hcsl clock/data multiplexer and fanout buffer. the device is designed for the multiplexing of high-frequency clock and data signals. the device has two differential, selectable clock/data inputs. the selected input signal is output at one differential hcsl output. each input pair accepts hcsl, lvds, and lvpecl levels. the ICS831721I is characterized to operate from a 3.3v power supply. guaranteed input, output-to-output and part-to-part skew characteristics make the ICS831721I ideal for those clock and data distribution applications demanding well-defined performance and repeatability. the ICS831721I supports the clock multiplexing and distribution of pci express generation 1, 2 and 3 clock signals. features ? 2:1 differential clock/data multiplexer with fanout two selectable, differential inputs each differential input pair can accept the following levels: hcsl, lvhstl, lvds and lvpecl one differential hcsl output maximum input/output clock frequency: 700mhz (maximum) maximum input/output data rate: 1400mb/s (nrz)lvcmos interface levels for all control inputs input skew: 55ps (maximum) part-to-part skew: 400ps (maximum) full 3.3v supply voltage available in lead-free (rohs 6) 16 tssop package -40c to 85c ambient operating temperature 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v dd nc gnd nclk1 clk1 v dd nclk0 clk0 iref sel v dd nq q v dd gnd noe ICS831721I 16 lead tssop 4.4mm x 5.0mm x 0.925mm package body g package top view block diagram q nq iref clk0 nclk0 clk1 nclk1 sel noe pulldown pullup pullup/down pulldown 0 1 pin assignment pullup/down pulldown
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 2 ?2011 integrated device technology, inc. table 1. pin descriptions note: pullup and pulldown refer to internal input resistors. see table 2, pin characteristics, for typical values. table 2. pin characteristics function tables table 3a. noe configuration table note: noe is an asynchronous control. table 3b. sel configuration table note: sel is an asynchronous control. number name type description 1 clk0 input pulldown non-inverting clock/data input 0. 2 nclk0 input pullup/pulldown inverting differential clock input 0. v dd /2 default when left floating. 3, 8, 11, 14 v dd power positive power supply. 4 clk1 input pulldown non-inverting clock/data input 1. 5 nclk1 input pullup/pulldown inverting differential clock input 1. v dd /2 default when left floating. 6, 10 gnd power power supply ground. 7ncunused no connect. 9 noe input pullup output enable. see table 3a for function. lvcmos/lvttl interface levels. 12, 13 q, nq output differential output pair. hcsl interface levels. 15 sel input pulldown input select. see table 3b for function. lvcmos/lvttl interface levels. 16 iref input an external fixed precision resistor (475 ? ) from this pin to ground provides a reference current used for the differential current-mode q, nq outputs. symbol parameter test conditions minimum typical maximum units c in input capacitance 4pf r pulldown input pulldown resistor 51 k ? r pullup input pulldown resistor 51 k ? input operation noe 0 output q, nq is enabled. 1 (default) output q, nq is in a high-impedance state. input selected input sel 0 (default) clk0, nclk0 1 clk1, nclk1
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 3 ?2011 integrated device technology, inc. absolute maximum ratings note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions beyond those listed in the dc characteristics or ac characteristics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. dc electrical characteristics table 4a. power supply dc characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c table 4b. lvcmos/lvttl input dc characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c table 4c. differential dc characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c note 1: v il should not be less than -0.3v. note 2: common mode input voltage is defined as v ih . item rating supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5v outputs, v o -0.5v to v dd + 0.5v package thermal impedance, ja 100.3c/w (0 mps) storage temperature, t stg -65 c to 150 c symbol parameter test conditions minimum typical maximum units v dd positive supply voltage 3.0 3.3 3.6 v i dd power supply current 26 ma symbol parameter test conditions minimum typical maximum units v ih input high voltage 2 v dd + 0.3 v v il input low voltage -0.3 0.8 v i ih input high current noe v dd = v in = 3.6v 5 a sel v dd = v in = 3.6v 150 a i il input low current noe v dd = 3.6v, v in = 0v -150 a sel v dd = 3.6v, v in = 0v -5 a symbol parameter test conditions minimum typical maximum units i ih input high current clk0, nclk0, clk1, nclk1 v dd = v in = 3.6v 150 a i il input low current clk0, clk1 v dd = 3.6v, v in = 0v -5 a nclk0, nclk1 v dd = 3.6v, v in = 0v -150 a v pp peak-to-peak voltage; note 1 0.15 1.3 v v cmr common mode input voltage; note 1, 2 0.5 v dd ? 0.85 v
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 4 ?2011 integrated device technology, inc. table 5. pci express jitter specifications, v dd = 3.3v 0.3v, ta= -40c to 85c note: the source generator used in the pci express jitter measurements is stanford research systems cg635 2.0ghz synthesized clock generator. note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the dev ice is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. for additional information, refer to the pci express application note section in the datasheet. note 1: peak-to-peak jitter after applying system transfer function for the common clock architecture. maximum limit for pci express g en 1 is 86ps peak-to-peak for a sample size of 10 6 clock periods. note 2: rms jitter after applying the two evaluation bands to the two transfer functions defined in the common clock architecture and reporting the worst case results for each evaluation band. maximum limit for pci express generation 2 is 3.1ps rms for t refclk_hf_rms (high band) and 3.0ps rms for t refclk_lf_rms (low band). note 3: rms jitter after applying system transfer function for the common clock architecture. this specification is based on the pci express base specification revision 0.7, october 2009 and is subject to change pending the final release version of the specification. note 4: this parameter is guaranteed by characterization. not tested in production. parameter symbol test conditions minimum typical maximum pcie industry specification units t j (pcie gen 1) phase jitter peak-to-peak note 1, 4 ? = 100mhz, evaluation band: 0hz - nyquist (clock requency/2) 6.77 11.2 86 ps t refclk_hf_rms (pcie gen 2) phase jitter rms; note 2, 4 ? = 100mhz, high band:1.5hz - nyquist (clock requency/2) 0.59 1.01 3.1 ps t refclk_lf_rms (pcie gen 2) phase jitter rms; note 2, 4 ? = 100mhz, low band: 10khz - 1.5hz 0.03 0.07 3.0 ps t refclk_rms (pcie gen 3) phase jitter rms; note 3, 4 ? = 100mhz, evaluation band: 0hz - nyquist (clock requency/2) 0.112 0.185 0.8 ps
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 5 ?2011 integrated device technology, inc. ac electrical characteristics table 5. hcsl ac characteristics, v dd = 3.3v 0.3v, t a = -40c to 85c note: electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the dev ice is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. the device will meet specifications after th ermal equilibrium has been reached under these conditions. note 1: measured from the differential input cross point to the differential output crossing point. note 2: defined as skew between input paths on the same device, using the same input signal levels, measured at one specific output at the differential cross points. note 3: this parameter is defined in accordance with jedec standard 65. note 4: defined as skew between outputs on different devices operating at the same supply voltage and with equal load conditions. usin g the same type of inputs on each device, the outputs are measured at the differential cross points. note 5: measurement taken from differential waveform. note 6: measurement from -150mv to +150mv on the differential wavefo rm (derived from q minus nq). the signal must be monotonic through the measurement region for rise and fall time. the 300mv measurement window is centered on the differential zero crossi ng. note 7: t stable is the time the differential clock must maintain a minimum 150mv differential voltage after rising/falling edges before it is allowed to drop back into the v rb 100 differential range. see parameter measurement information section. note 8: measurement taken from single-ended waveform. note 9: defined as the maximum instantaneous voltage including overshoot. see parameter measurement information section. note 10: defined as the minimum instantaneous voltage including undershoot. see parameter measurement information section. note 11: measured at crossing point where the instantaneous voltage value of the rising edge of qx equals the falling edge of nqx. see parameter measurement information section note 12: refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. refers to a ll crossing points for this measurement. see parameter measurement information section. note 13: defined as the total variation of all crossing voltage of rising q and falling nq. this is the maximum allowed variance in the v cross for any particular system. see parameter measurement information section. note 14: input duty cycle must be 50%. note 15: q, nq output measured differentially. see mux isolation diagram in parameter measurement information section. symbol parameter test conditions minimum typical maximum units f out output frequency 700 mhz t jit buffer additive phase jitter, rms; refer to additive phase jitter plot 100mhz, integration range: 12khz ? 20mhz 0.314 0.337 ps t pd propagation delay, note 1 any clkx, nclkx to q, nq 2 2.4 ns tsk(i) input skew; note 2 55 ps tsk(pp) part-to-part skew; note 3, 4 400 ps edge rate rise/fall edge rate; note 5, 6 0.6 4.0 v/ns v rb ringback voltage; note 5, 7 -100 100 v v max absolute max output voltage; note 8, 9 1150 mv v min absolute min output voltage; note 8, 10 -300 mv v cross absolute crossing voltage; note 8, 11, 12 250 550 mv ? v cross total variation of v cross over all edges; note 8, 11, 13 140 mv odc output duty cycle; note 14 f out < 312.5mhz 46 54 % f out > 312.5mhz 43 57 % mux isol mux isolation; note 15 ? = 100mhz 80 db
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 6 ?2011 integrated device technology, inc. additive phase jitter the spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dbc phase noise. this value is normally expressed using a phase noise plot and is most often the specified plot in many applications. phase noise is defined as the ratio of the noise power present in a 1hz band at a specified offset from the fundamental frequency to the power value of the fundamental. this ratio is expressed in decibels (dbm) or a ratio of the power in the 1hz band to the power in the fundamental. when the required offset is specified, the phase noise is called a dbc value, which simply means dbm at a specified offset from the fundamental. by investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. it is mathematically possible to calculate an expected bit error rate given a phase noise plot. as with most timing specifications, phase noise measurements has issues relating to the limitations of the equipment. often the noise floor of the equipment is higher than the noise floor of the device. this is illustrated above. the device meets the noise floor of what is shown, but can actually be lower. the phase noise is dependent on the input source and measurement equipment. the source generator is the rhode & schwarz sma 100a signal generator 9khz ? 6ghz. phase noise is measured with the agilent e5052a signal source analyzer. additive phase jitter @ 100mhz 12khz to 20mhz = 0.314ps (typical) ssb phase noise dbc/hz offset from carrier frequency (hz)
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 7 ?2011 integrated device technology, inc. parameter measurement information 3.3v hcsl output load ac test circuit differential input level propagation delay 3.3v hcsl output load ac test circuit mux_isolation part-to-part skew 475 ? 33 ? 50 ? 50 ? 33 ? 49.9 ? 49.9 ? hcsl gnd 2pf 2pf qx nqx 0v iref v dd 3.3v0.3v v cmr cross points v pp v dd gnd nclk[0:1] clk[0:1] t pd nclk[0:1] clk[0:1] nq q 475 ? 50 ? 50 ? hcsl gnd 0v scope iref v dd this load condition is used for i dd, t sk(pp), t sk(i), t pd and tjit measurements. 3.3v0.3v amplitude (db) a0 spectrum of output signal q mux _isol = a0 ? a1 (fundamental) frequency ? mux selects static input mux selects active input clock signal a1 t sk(pp) part 1 part 2 qx nqx qx nqy
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 8 ?2011 integrated device technology, inc. parameter measurement information, continued single-ended measurement points for absolute cross point/swing differential measurement points for rise/fall edge rate single-ended measurement points for delta cross point differential measurement points for ringback input skew v cross_max v cross_min v max v min nq q q - nq -150mv +150mv 0.0v fall edge rate rise edge rate ? v cross nq q t stable v rb q - nq -150mv v rb = -100mv v rb = +100mv +150mv 0.0v v rb t stable t pd2 t pd1 tsk(i) = |t pd1 - t pd2 | tsk(i) nclk1 clk1 nq q nclk0 clk0
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 9 ?2011 integrated device technology, inc. applications information recommendations for unused input pins i nputs: lvcmos control pins all control pins have internal pullups and pulldowns; additional resistance is not required but can be added for additional protection. a 1k ? resistor can be used. clk/nclk inputs for applications not requiring the use of the differential input, both clk and nclk can be left floating. though not required, but for additional protection, a 1k ? resistor can be tied from clk to ground. wiring the differential input to accept single-ended levels figure 1 shows how a differential input can be wired to accept single ended levels. the reference voltage v ref = v cc /2 is generated by the bias resistors r1 and r2. the bypass capacitor (c1) is used to help filter noise on the dc bias. this bias circuit should be located as close to the input pin as possible. the ratio of r1 and r2 might need to be adjusted to position the v ref in the center of the input voltage swing. for example, if the input clock swing is 2.5v and v cc = 3.3v, r1 and r2 value should be adjusted to set v ref at 1.25v. the values below are for when both the single ended swing and v cc are at the same voltage. this configuration requires that the sum of the output impedance of the driver (ro) and the series resistance (rs) equals the transmission line impedance. in addition, matched termination at the input will attenuate the signal in half. this can be done in one of two ways. first, r3 and r4 in parallel should equal the transmission line impedance. for most 50 ? applications, r3 and r4 can be 100 ? . the values of the resistors can be increased to reduce the loading for slower and weaker lvcmos driver. when using single-ended signaling, the noise rejection benefits of differential signaling are reduced. even though the differential input can handle full rail lvcmos signaling, it is recommended that the amplitude be reduced. the datasheet specifies a lower differential amplitude, however this only applies to differential signals. for single-ended applications, the swing can be larger, however v il cannot be less than -0.3v and v ih cannot be more than v cc + 0.3v. though some of the recommended components might not be used, the pads should be placed in the layout. they can be utilized for debugging purposes. the datasheet specifications are characterized and guaranteed by using a differential signal. figure 1. recommended schematic for wiring a differential input to accept single-ended levels
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 10 ?2011 integrated device technology, inc. pci express a pplication note pci express jitter analysis methodology models the system response to reference clock jitter. the block diagram below shows the most frequently used common clock architecture in which a copy of the reference clock is provided to both ends of the pci express link. in the jitter analysis, the transmit (tx) and receive (rx) serdes plls are modeled as well as the phase interpolator in the receiver. these transfer functions are called h1, h2, and h3 respectively. the overall system transfer function at the receiver is: the jitter spectrum seen by the receiver is the result of applying this system transfer function to the clock spectrum x(s) and is: in order to generate time domain jitter numbers, an inverse fourier transform is performed on x(s)*h3(s) * [h1(s) - h2(s)]. pci express common clock architecture for pci express gen 1 , one transfer function is defined and the evaluation is performed over the entire spectrum: dc to nyquist (e.g for a 100mhz reference clock: 0hz ? 50mhz) and the jitter result is reported in peak-peak. pcie gen 1 magnitude of transfer function for pci express gen 2 , two transfer functions are defined with 2 evaluation ranges and the final jitter number is reported in rms. the two evaluation ranges for pci express gen 2 are 10khz ? 1.5mhz (low band) and 1.5mhz ? nyquist (high band). the plots show the individual transfer functions as well as the overall transfer function ht. pcie gen 2a magnitude of transfer function pcie gen 2b magnitude of transfer function for pci express gen 3 , one transfer function is defined and the evaluation is performed over the entire spectrum. the transfer function parameters are different from gen 1 and the jitter result is reported in rms. pcie gen 3 magnitude of transfer function for a more thorough overview of pci express jitter analysis methodology, please refer to idt application note pci express reference clock requirements. ht s () h 3 s () h 1 s () h 2 s () ? [] = ys () xs () h 3 s () h 1 s () h 2 s () ? [] =
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 11 ?2011 integrated device technology, inc. recommended termination figure 3a is the recommended source termination for applications where the driver and receiver will be on a separate pcbs. this termination is the standard for pci express? and hcsl output types. all traces should be 50 ? impedance single-ended or 100 ? differential. figure 3a. recommended source termination (where the driver and receiver will be on separate pcbs) figure 3b is the recommended termination for applications where a point-to-point connection can be used. a point-to-point connection contains both the driver and the receiver on the same pcb. with a matched termination at the receiver, transmission-line reflections will be minimized. in addition, a series resistor (rs) at the driver offers flexibility and can help dampen unwanted reflections. the optional resistor can range from 0 ? to 33 ? . all traces should be 50 ? impedance single-ended or 100 ? differential. figure 3b. recommended termination (where a point-to-point connection can be used) 0-0.2" pci express l1 l1 1-14" driver rs 0.5" max l3 l4 l2 l2 49.9 +/- 5% 22 to 33 +/-5% rt l3 l4 l5 0.5 - 3.5" l5 connector pci express add-in card pci express 0-0.2" pci express 0-0.2" 0-18" l1 l1 rs driver 0.5" max l3 l3 l2 l2 49.9 +/- 5% 0 to 33 0 to 33 rt
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 12 ?2011 integrated device technology, inc. differential clock input interface the clk /nclk accepts lvds, lvpecl, lvhstl, hcsl and other differential signals. both signals must meet the v pp and v cmr input requirements. figures 2a to 2f show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example, in figure 2a, the input termination applies for idt open emitter lvhstl drivers. if you are using an lvhstl driver from another vendor, use their termination recommendation. figure 2a. clk/nclk input driven by an idt open emitter lvhstl driver figure 2c. clk/nclk input driven by a 3.3v lvpecl driver figure 2e. clk/nclk input driven by a 3.3v lvds driver figure 2b. clk/nclk input driven by a 3.3v hcsl driver figure 2d. clk/nclk input driven by a 3.3v lvpecl driver r1 50 ? r2 50 ? 1.8v zo = 50 ? zo = 50 ? clk nclk 3.3v lvhstl idt lvhstl driver differential input r3 125 r4 125 r1 84 r2 84 3.3v zo = 50 ? zo = 50 ? clk nclk 3.3v 3.3v lvpecl differential input 3.3v r1 100 lvds clk nclk 3.3v differential input zo = 50 ? zo = 50 ? hcsl *r3 33 ? *r4 33 ? clk nclk 3.3v 3.3v zo = 50 ? zo = 50 ? differential input r1 50 ? r2 50 ? *optional ? r3 and r4 can be 0 ? clk nclk differential input lvpecl 3.3v zo = 50 ? zo = 50 ? 3.3v r1 50 ? r2 50 ? r2 50 ?
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 13 ?2011 integrated device technology, inc. power considerations this section provides information on power dissipation and junction temperature for the ics831752i. equations and example calculations are also provided. 1. power dissipation. the total power dissipation for the ics831752i is the sum of the core power plus the analog power plus the power dissipated in the load(s). the following is the power dissipation for v dd = 3.3v + 0.3v = 3.6v, which gives worst case results. power (core) max = v dd_max * i dd_max = 3.6v * 26ma = 93.6mw power (outputs) max = 46.8mw/loaded output pair total power_ max (3.63v, with all outputs switching) = 93.6mw + 46.8mw = 140.4mw 2. junction temperature. junction temperature, tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. the maximum recommended junction temperature is 125c. limiting the internal transistor junction temperature, tj, to 125c ensures that the bond wire and bond pad temperature remains below 125c. the equation for tj is as follows: tj = ja * pd_total + t a tj = junction temperature ja = junction-to-ambient thermal resistance pd_total = total device power dissipation (example calculation is in section 1 above) t a = ambient temperature in order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance ja must be used. assuming no air flow and a multi-layer board, the appropriate value is 100.3c/w per table 6 below. therefore, tj for an ambient temperature of 85c with all outputs switching is: 85c + 0.140w * 100.3c/w = 99c. this is below the limit of 125c. this calculation is only an example. tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of board (multi-layer). table 6. thermal resistance ja for 16 lead tssop, forced convection ja by velocity meters per second 012.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 14 ?2011 integrated device technology, inc. the purpose of this section is to calculate power dissipation on the ic per hcsl output pair. hcsl output driver circuit and termination are shown in figure 4. figure 4. hcsl driver circuit and termination hcsl is a current steering output which sources a maximum of 17ma of current per output. to calculate worst case on-chip power dissipation, use the following equations which assume a 50 ? load to ground. the highest power dissipation occurs when v dd _ max . power = (v dd_max ? v out ) * i out , since v out ? i out * r l = (v dd_max ? i out * r l ) * i out = (3.6v ? 17ma * 50 ? ) * 17ma total power dissipation per output pair = 46.8mw v dd v out r l 50 ? ic ? i out = 17ma r ref = 475 ? 1%
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 15 ?2011 integrated device technology, inc. package outline and package dimensions table 7. ja vs. air flow table for a 16 lead tssop transistor count the transistor count for ICS831721I is: 632 package outline and package dimensions package outline - g suffix for 16 lead tssop table 8. package dimensions for 16 lead tssop reference document: jedec publication 95, mo-153 ja vs. air flow meters per second 012.5 multi-layer pcb, jedec standard test boards 100.3c/w 96.0c/w 93.9c/w all dimensions in millimeters symbol minimum maximum n 16 a 1.20 a1 0.05 0.15 a2 0.80 1.05 b 0.19 0.30 c 0.09 0.20 d 4.90 5.10 e 6.40 basic e1 4.30 4.50 e 0.65 basic l 0.45 0.75 0 8 aaa 0.10 all dimensions in millimeters symbol minimum maximum
ICS831721I data sheet differential clock/data multiplexer ics831721agi revision a august 19, 2011 16 ?2011 integrated device technology, inc. ordering information table 9. ordering information note: parts that are ordered with an ?lf? suffix to the part number are the pb-free configuration and are rohs compliant part/order number marking package shipping packaging temperature 831721agilf 31721ail lead-free, 16 lead tssop tube -40 c to 85 c 831721agilft 31721ail lead-free, 16 lead tssop 2500 tape & reel -40 c to 85 c while the information presented herein has been checked for both accuracy and reliability, integrated device technology (idt) a ssumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or l icenses are implied. this product is intended for use in normal commercial and industrial applications. any other applications, such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not aut horize or warrant any idt product for use in life support devices or critical medical instruments.
ICS831721I data sheet differential clock/data multiplexer disclaimer integrated device technology, inc. (idt) and its subs idiaries reserve the right to modify the products and/or specif ications described herein at any time and at idt?s sole discretion. all information in this document, including descriptions of product features and performance, is s ubject to change without notice. performance specifications and the operating parameters of the described products ar e determined in the independent state and are not guaranteed to perform the same way when installed in customer products. the information containe d herein is provided without re presentation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of idt?s products for any particular purpose, an imp lied warranty of merchantability, or non-infringement of the in tellectual property rights of others. this document is presented only as a guide and does not convey any license under intellectual property right s of idt or any third parties. idt?s products are not intended for use in life support systems or similar devices where the failure or malfunction of an idt p roduct can be reasonably expected to significantly affect the health or safety of users. anyone using an idt product in such a manner does so at their own risk, absent an express, written agreement by idt. integrated device technology, idt and the idt logo are registered trademarks of idt. other trademarks and service marks used he rein, including protected names, logos and designs, are the property of idt or their respective third party owners. copyright 2011. all rights reserved. 6024 silver creek valley road san jose, california 95138 sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 www.idt.com/go/contactidt technical support netcom@idt.com +480-763-2056 we?ve got your timing solution

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